STMicroelectronics, ARM and Cadence boost Accellera Systems Initiative

STMicroelectronics has entered into collaboration with ARM and Cadence Design Systems to increase model and tool interoperability for electronic system-level (ESL) design at the transaction level. This partnership also includes three new contributions to the SystemC Language Working Group of the Accellera Systems Initiative. The contributions consist of fully working application programming interfaces (API) and implementations, as well as documentation and examples, released under an Apache 2.0 open-source licence. 

The joint work includes new interfaces for interrupt modelling, which allow seamless integration of models from different companies; application programming interfaces for register introspection that enables tool interoperability to seamlessly display and update register values; and new approaches for memory-map modelling that improve users’ productivity during debugging of virtual platforms for hardware/software multicore systems.

“These new interfaces are crucial to strengthening the ESL ecosystem. As a step towards interoperability driven by ST, ARM and Cadence, these proposed standards dramatically reduce risks and efforts associated with the integration of virtual prototypes. Eliminating the need for adapters will increase virtual prototype simulation performances, enable sooner and faster hardware-software integration, and therefore improve product time-to-market,” said Philippe Magarshack, Executive VP, Design Enablement & Services, STMicroelectronics.

With these new contributions, ST, ARM and Cadence expect integration of SystemC models in virtual prototypes and will be significantly improved for all users, enabling the models’ quick and efficient deployment. In addition, standard interfaces between models and tools will extend hardware/software integration and debug capabilities using appropriate tools.