HiSilicon partners with Synopsys for improving Design Objectives

Synopsys has announced that HiSilicon Technologies has taped out a 50+ million instance ARM Cortex-A15 processor-based system-on-a-chip (SoC) using a key component of Synopsys’ Galaxy Implementation Platform which is an IC Compiler. This has led to the improvement of clock speed by 100 MHz through IC Compiler multisource clock tree synthesis (CTS) technology.

Antun Domic, Senior Vice-President & General Manager, Synopsys Implementation Group, said, "HiSilicon Technologies has a growing reputation as a leading chipset solution provider for the wireless and networking markets. Our partnership with HiSilicon Technologies has benefited both companies by shaping unique technologies in IC Compiler which have contributed to its growing use in the physical design space."
 
"At HiSilicon, we continually innovate to deliver complex SoC solutions that are well differentiated in terms of performance and functionality. We have long recognized the importance of working with leading-edge partners like Synopsys to enable us to achieve our design objectives. On this multi-million instance SoC tapeout, we used the latest technologies in the Galaxy Implementation Platform to develop a correlated and predictable design closure flow that met our aggressive performance targets for on-time delivery," said Teresa He, President, HiSilicon Technologies.
 
The 50+ million instance HiSilicon SoC targeting the wireless chipset market contains multiple ARM Cortex-A15 processors, peripheral logic and memories. It was implemented hierarchically and fabricated on a TSMC 28HPM process using TSMC standard cell libraries and fast cache instance memories. HiSilicon leveraged the Synopsys High Performance Core (HPC) methodology on this tapeout, including faster ECO closure with PrimeTime signoff driven ECO guidance.