AMD unveils New Graphics Architecture

AMD has unveiled preliminary details of its forthcoming GPU architecture – Vega. Conceived and executed over five years, Vega architecture enables new possibilities in PC gaming, professional design and machine intelligence that traditional GPU architectures have not been able to address effectively. Data-intensive workloads are becoming the new normal, and the parallel nature of the GPU lends itself ideally to tackling them. However, processing these huge new data sets require fast access to massive amounts of memory. The Vega architecture's revolutionary memory subsystem enables GPUs to address very large data sets spread across a mix of memory types. The high-bandwidth cache controller in Vega-based GPUs can access on-package cache and off-package memories in a flexible, programmable fashion using fine-grained data movement.

“It is incredible to see GPUs being used to solve gigabyte-scale data problems in gaming to exabyte-scale data problems in machine intelligence. We designed the Vega architecture to build on this ability, with the flexibility to address the extraordinary breadth of problems GPUs will be solving not only today but also five years from now. Our high-bandwidth cache is a pivotal disruption that has the potential to impact the whole GPU market,” said Raja Koduri, Senior Vice-President & Chief Architect, Radeon Technologies Group, AMD.

The Vega architecture enables a new memory hierarchy for GPUs. This radical new approach comes in the form of a new high-bandwidth cache and its controller. The cache features leading-edge HBM2 technology which is capable of transferring terabytes of data every second, doubling the bandwidth-per-pin over the previous generation HBM technology. HBM2 also enables much greater capacity at less than half the footprint of GDDR5 memory. Vega architecture is optimized for streaming very large data sets and can work with a variety of memory types with up to 512 TB of virtual address space.

Today’s games and professional applications make use of incredibly complex geometry enabled by the extraordinary increase in the resolutions of data acquisition devices.  The hundreds of millions of polygons in any given frame have meshes so dense that there are often many polygons being rendered per pixel. Vega’s next-generation geometry pipeline enables the programmer to extract incredible efficiency in processing this complex geometry, while also delivering more than 200% of the throughput-per-clock over previous Radeon architectures. It also features improved load-balancing with an intelligent workload distributor to deliver consistent performance.

At the core of the Vega architecture is a new, next-generation compute engine built on flexible compute units that can natively process 8-bit, 16-bit, 32-bit or 64-bit operations in each clock cycle.These compute units are optimized to attain significantly higher frequencies than previous generations and their support of variable data types makes the architecture highly versatile across workloads.

The new Vega pixel engine employs a Draw Stream Binning Rasterizer, designed to improve performance and power efficiency. It allows for “fetch once, shade once” of pixels through the use of a smart on-chip bin cache and early culling of pixels invisible in a final scene. Vega’s pixel engine is now a client of the onboard L2 cache, enabling considerable overhead reduction for graphics workloads which perform frequent read-after-write operations.

GPU products based on the Vega architecture are expected to be shipped in the first half of 2017.